Browsing by Author "Reddy, B. Naresh Kumar."

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    An energy-efficient FPGA accelerator for transformer inference using layer-wise precision optimization
    (Elsevier B.V., 2026-09-06) Eiswar S, Darun; N, Pugalbharani; Bharatula, Sitadevi; Reddy, B. Naresh Kumar.
    Abstract FPGA transformer accelerators routinely fix their multiply-accumulate (MAC) accumulators at 32 bits, echoing a theoretical 25–27-bit worst case for INT8 BERT-base matrix multiplication that has never been checked against actual per-layer behavior. We provide a transformer-specific layer-level study, profiling 215 linear layers across BERT-base, TinyBERT-4L, DistilBERT-base, ALBERT-base-v2, and ELECTRA-small-discriminator over WikiText-2 samples via PyTorch forward-hook INT8 simulation that tracks the true partial-sum accumulation trajectory (not only the final dot-product value) with a 2-bit margin. Across these 215 profiled layers, the maximum observed accumulator requirement is 20 bits under the specified profiling conditions, and 500 SST-2 samples show zero prediction changes, with δ=2 bits the best-performing margin among those tested. Synthesized on the Zynq™ UltraScale+™ MPSoC ZCU104, a 16-bit MAC cuts flip-flops 39% and LUTs 17% versus a 32-bit baseline while exceeding 400 MHz; a per-layer-instance resource lower bound for a 73-layer BERT-base array projects 34.5% fewer flip-flops and 15.4% fewer LUTs.
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    Analyzing Fully Depleted SOI NC-MOSFET for Enhanced Bio-Sensor and Digital Circuit Applications
    (John Wiley and Sons Ltd, 2025-03-18) Kumar, Vydha Pradeep; Panda, Deepak Kumar; Kumar, Aruru Sai; Reddy, B. Naresh Kumar.; Reddy, Ch. Rama Prakasha
    The proposed research paper focuses on the study of fully depleted silicon (Si)-on-insulator negative capacitance metal oxide-semiconductor field-effect transistor (FDSOI-NC-MOSFET) performance for biosensor and digital circuit applications. The study mainly aims to use ferroelectric (FE) material to improve the performance and efficiency of FDSOI-NC-MOSFETs compared to conventional planar MOSFETs. Using TCAD software, the proposed device is simulated and analyzed under various parameter conditions (parameters like temperature, channel thickness, input supply voltages, and channel doping levels). Later, the proposed device is also designed for different biomolecular structures to analyze the selectivity and sensitivity behavior of the device. Sensitivity is the change in electrical characteristics in response to applied external stimuli or parameters like current and voltages. Variations in these parameters will affect the operating region of the device, thereby, the choice of parameters in achieving the best performance will depend on the operating conditions and device applications. NC-MOSFET with FE materials can obtain an acceptable on/off current ratio by lowering the off current and can achieve an adequate subthreshold swing (SS), thus, observed that the NC-MOSFET device has enhanced performance and transfer characteristics in comparison to planar MOSFET. For K = 4, at an input voltage of 0.25 V, the Ion/Ioff ratio was 6.21 × 105 and the sensitivity was 6.20 × 107 and at 0.5 V, these values rise to 8.07 × 105 and 8.073 × 107, respectively. Similarly for K = 6 and at an input voltage of 0.25 V, we observed an Ion/Ioff ratio is 1.5 × 107 and a sensitivity of 1.52 × 109. When the input voltage was increased to 0.5 V, the Ion/Ioff ratio improved to 2.07 × 107 and the sensitivity increased to 2.073 × 109. From these analyses, it is apparent that as the K-values increase at a given input voltage, both the Ion/Ioff ratio and the sensitivity also increase significantly. Finally, in this paper, we also demonstrated the implementation and simulation of digital logic gates using the proposed NC-MOSFET device, supporting circuit-level design applications. Copyright
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    RISC-Based Secure Architecture for Data-Flow Integrity in Modern Embedded and Edge Systems
    (Multidisciplinary Digital Publishing Institute (MDPI), 2026-08-06) Kannaiah,K; Jogi, Srinivasulu; Reddy, B. Naresh Kumar.
    Modern embedded systems are vulnerable to complex data-oriented attacks that subvert not only existing control-flow integrity protections but also have dire implications on safety-critical applications. To overcome this challenge, this work proposes a secure RISC-based architecture that incorporates hardware-assisted Data-Flow Integrity (DFI) enforcement into the processor pipeline. The architecture uses tag-based metadata propagation, a Security Monitor Unit, and compiler support for static analysis in order to ensure the validity of dynamic data flows without affecting execution. A complete RTL prototype was designed and tested with MiBench and CoreMark. Results show an average performance overhead of 11.3% and a logic utilization increase of <9.2% on FPGAs, while achieving 100% detection of all attempted pointer corruption and data tampering attacks. These results indicate the efficacy of the lightweight security-aware RISC architecture as a feasible compromise between security, performance, and hardware expense in today’s embedded systems.