Browsing by Author "Kumar, Aruru Sai"

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    Analyzing Fully Depleted SOI NC-MOSFET for Enhanced Bio-Sensor and Digital Circuit Applications
    (John Wiley and Sons Ltd, 2025-03-18) Kumar, Vydha Pradeep; Panda, Deepak Kumar; Kumar, Aruru Sai; Reddy, B. Naresh Kumar.; Reddy, Ch. Rama Prakasha
    The proposed research paper focuses on the study of fully depleted silicon (Si)-on-insulator negative capacitance metal oxide-semiconductor field-effect transistor (FDSOI-NC-MOSFET) performance for biosensor and digital circuit applications. The study mainly aims to use ferroelectric (FE) material to improve the performance and efficiency of FDSOI-NC-MOSFETs compared to conventional planar MOSFETs. Using TCAD software, the proposed device is simulated and analyzed under various parameter conditions (parameters like temperature, channel thickness, input supply voltages, and channel doping levels). Later, the proposed device is also designed for different biomolecular structures to analyze the selectivity and sensitivity behavior of the device. Sensitivity is the change in electrical characteristics in response to applied external stimuli or parameters like current and voltages. Variations in these parameters will affect the operating region of the device, thereby, the choice of parameters in achieving the best performance will depend on the operating conditions and device applications. NC-MOSFET with FE materials can obtain an acceptable on/off current ratio by lowering the off current and can achieve an adequate subthreshold swing (SS), thus, observed that the NC-MOSFET device has enhanced performance and transfer characteristics in comparison to planar MOSFET. For K = 4, at an input voltage of 0.25 V, the Ion/Ioff ratio was 6.21 × 105 and the sensitivity was 6.20 × 107 and at 0.5 V, these values rise to 8.07 × 105 and 8.073 × 107, respectively. Similarly for K = 6 and at an input voltage of 0.25 V, we observed an Ion/Ioff ratio is 1.5 × 107 and a sensitivity of 1.52 × 109. When the input voltage was increased to 0.5 V, the Ion/Ioff ratio improved to 2.07 × 107 and the sensitivity increased to 2.073 × 109. From these analyses, it is apparent that as the K-values increase at a given input voltage, both the Ion/Ioff ratio and the sensitivity also increase significantly. Finally, in this paper, we also demonstrated the implementation and simulation of digital logic gates using the proposed NC-MOSFET device, supporting circuit-level design applications. Copyright
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    Efficient computation and design of high speed double precision Vedic multiplier architecture
    (Nature Research, 2026-02-05) Kumar, Aruru Sai; Sahitya G.; Kusuma, Rambabu; Krishna, M. Sankush; Reddy, B. Naresh Kumar; Tripathi, Suman Lata
    Efficient multiplication and addition of floating-point numbers play a crucial role in digital signal processing applications. To achieve high computational performance with minimal resource utilization, an optimized multiplication approach is essential. Vedic mathematics encompasses the utilization of 16 sutras or algorithms. This paper presents a double-precision floating-point multiplier of 53-bit mantissa based on Vedic mathematics. The proposed architecture performs multiplication in three stages: sign generation, exponent generation, and mantissa multiplication. The Urdhva Tiryakbhyam sutra is employed for mantissa computation owing to its high efficiency and reduced hardware complexity compared to conventional techniques. The proposed multiplier design is implemented using Verilog HDL on Vivado 2022.2. Experimental results demonstrate a significant reduction in critical path delay and logic utilization compared to existing floating-point and Vedic-based multipliers, while maintaining a favorable power consumption trend. The CNN implementation employing the proposed Vedic double-precision floating-point multiplier achieves the lowest inference latency and power consumption while maintaining identical classification accuracy compared to conventional IEEE-754 and existing Vedic-based multiplier designs. Hardware realization on a Zynq FPGA device further confirms the superiority of the proposed architecture in terms of power, delay and on-board component utilization.